Lab 6 - EE 421L
Digital Integrated Circuit Design
Author:
Matthew Meza
Email:
mezam11@unlv.nevada.edu
October 19, 2015
Design, layout, and simulation of a
CMOS Nand gate, XOR gate, and Full-Adder!
Pre-lab work
- Back-up
all of your work from the lab and the course.
- Go
through Cadence Tutorial 4 seen here.
- Read through the lab in
its entirety before starting to work on it
Proof of Prelab
 |
Schematic of NAND gate
 |
Layout of Nand Gate
 |
Symbol used for nand gate!
 |
Lab Description
In
this lab we will design, layout, and simulate an inverter made of NMOS
and PMOS MOSFETs in ON's C5 Process.
After the layout, we will plot characterization curves with different
loads!
Lab Requirement
- Draft
the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR
gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
- Create
layout and symbol views for these gates showing that the cells DRC
and LVS without errors
- ensure
that your symbol views are the commonly used symbols (not boxes!) for
these gates with your initials in the middle of the symbol
- ensure
all layouts in this lab use standard cell frames that snap together
end-to-end for routing vdd! and gnd!
- use a standard
cell height
taller than you need for these gates so that it can be used for more
complicated layouts in the future
- ensure
gate inputs, outputs, vdd!, and gnd! are all routed on metal1
- Use
cell names that include your initials and the current year/semester,
e.g. NAND_jb_f19 (if it were fall 2019)
- Using
Spectre simulate the logical operation of the gates for all 4 possible
inputs (00, 01, 10, and 11)
- comment
on how timing of the input pulses can cause glitches in the output of a
gate
- Using
these gates, draft the schematic of the full adder seen below
- Create
a symbol for this full-adder (example)
- Simulate,
using Spectre, the operation of the full-adder using this symbol
- Layout
the full-adder by placing the 5 gates end-to-end so that vdd! and gnd!
are routed
- full-adder
inputs and outputs can be on metal2 but not metal3
- DRC
and LVS your full adder design
-
Post-Lab Excercises
2-Input
Nand-Gate 6u/0.6u
Schematic
with size of 6u/0.6u
Notice the size difference from the Pre-Lab
|
Layout of
the Nand-Gate
Notice the size difference from the Pre-Lab
|
Proof of DRC/LVS
 |
Symbol for NAND Gate
 |
2-Input
XOR gate using 6u/0.6u
XOR gate
Schematic
|
Layout
|
XOR DRC and LVS
 |
XOR Symbol
 |
Simulations of gates!
Schematic of
logic's being simulated
|
Inverter Sim-Logic
|
NAND Sim-Logic
 |
XOR Sim-Logic
 |
Notice how the NAND and XOR sim logic have
glitches on the switching points. This is because these gates are
not
ideal and have internal time delays. The internal time
delays cause the output to begin to change and then return to its
correct state.
Full Adder Schematic, Layout, Symbol, and
Simulation
Schematic!
Layout!
Notice the gnd and vdd rails at the top and bottom of the layout,
they extend the full length of the layout. Also notice how all the
routing
is done on the metal 1 and metal 2 layers.
Proof of DRC and LVS!
Simulations of the Full-Adder can be seen above in
the Sim-Logic section!
Notice the
glitches at the output /s and /cout. This is because these gates are
not
ideal and have internal time delays. The internal time
delays cause the output to begin to change and then return to its
correct state.
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